Welcome to OpenFPGA-Softcores’ documentation!

The goal of the project is to co-architect open-source processors (or soft-cores) and heterogeneous FPGA targets using the open-source OpenFPGA framework. The proposed platform acts as a Python API, wrapping EDA tools, for fast and accurate design space exploration.

The main objectives are to provide:

1. A methodology to improve soft-core mapping on FPGA targets.

2. Packer, placer and router analysis, to identify path bottlenecks related to the soft-core RTL description.

3. Better domain-specific FPGA architectures tuned according to the design and application requirements.

Fig. 1 OpenFPGA-Softcores platform overview.

Note

This project is under active development.

User Guide

• 1. Getting Started
  • 1.1. Installation
  • 1.2. Virtual Python Environment
• 2. Tools
  • 2.1. run-softcore
  • 2.2. run-dse
  • 2.3. report-yosys-vpr
  • 2.4. report-place-timing
  • 2.5. report-route-paths
• 3. Analysis
  • 3.1. Multiple Task Launchers
  • 3.2. analyze-yosys-vpr
  • 3.3. analyze-placing

Reference Manual

• 1. Parsers API
  • 1.1. Yosys Parsers
  • 1.2. VPR Parsers
• 2. Softcores API
  • 2.1. PicoRV32
• 3. Generators API
  • 3.1. OpenFPGA Task Generator

Indices and tables

• Index

• Module Index

• Search Page